M202 — Logic Latch Module

M202 LoGIc LATCH MQDULE The M202 Logic Latch module accepts three momentary pushbutton inputs and stores or Tatches the status of the pushbutton depressed . Only one of the three status outputs wili be latched at any one time . 5 ;= 1 + 0'1? 27'0 / Additionally an alternate action type Iatch is provided for fourth pushbutton input. ,eD #Tuqiuc ~78 4360 70( Nat AaV Tc 6 =9 A6t n; 50 501n T0 nj 6 670722 (in St72: A' Inputs a0t e - ) :Heuod 270 27082;G76 `1 529n1 1f 270.321109 F_jjtso 4J63 P70" ? 32- C3'8in: 0 ) = 7J? 67 ' - Cc-' The input circuit configuration is identical for all four pushbutton inputs. With the control inputs floating, the open-circuit voltage at the control pins is approximately 19 volts The inputs are protected against inadvertent high-voltage application and may be sa fely opera- ted at potentials UP to +30 volts An R/c network guards the inputs against the effects of switch bounce . Each input circuit is followed by an inverting Schmitt trigger. Uf" [ 9k2_? nmob Ija 4J Dre 276 312 5'7) en 7Ubn? 052764? 'j" {) In order IO affect change of status, logic "0" is applied t0 any of the inputs, ranging from to +2 volts, and having minimum duration of 100 milliseconds W1P0J Cc' 'JA BA Anterlocking Three Pushbutton Control Legic nia 6 1.35 W'gc: 67 , 6| ! > Oya 1700(73 90) Zluan: The function of the three control inputs at pins 2, B and 13 can be compared t0 that of bank of three interlocking pushbutton switches, where the operation of any one switch causes the other Wo to release . 92u 80 (0 150q8 82s1lov 2r,iOE-svlbzor This operation is achieved in the following way F1 F -a ona bewueiino? CUJ c 0ui5ae- @ 94T u2 is BCD t0 decimal decoder , used as priority decoder . Of the four available binary inputs, only the first three are being used, namely A (pin 15) , B (pin 14) and c (pin 13) . As these inputs are individually addressed with logic "1" level originating from the outputs of U1 , the decoder wili produce logic "0" decimal output signal at output (pin 2) , output 2 (pin 3) or output (pin 5) f more than one input is addressed simultaneously, no decoder output wiii result. 4Q'Uo 407' 7f KO PL"( 04 enivinb naa The three decimal outputs are combined via an OR gate consisting of CR9, CRIO and CRII, the output of which triggers one-shot multivibrator configured from [Wo of the four gates con tained in u3 . negative-going pulse of about 20 milliseconds duration is generated at u3_ pin Routed via CR12, this pulse feeds the CLEAR inputs of the R/s type latches U4A, ULB and USA . b9l GnoGto3n1 Traj (cuondi I5'inoica rommoj T0"'Ol? 4 :) 1o @ninone 'd 7olang er{IEE-FO I-1

WAAD-BECX SYSTems LTD; OTJ evateye >iOze-QAW

M202 LOGIc LATCH_MODULE The M202 Logic Latch module accepts three momentary pushbutton inputs and tores Ia [ches the status the pushbutton depressed Only one the three status OUIPUts will be latched at any one time Additionally an alternate action type Iatch provided for pushbutton input. 4 |a^ 50 Sna Inputs ~Cuo7o 65 ` ) fourth The input circuit configuration identica for al four pushbutton inputs With the control inputs floating, the open-circuit voltage the controi pins approximately volts.

The inputs are protected against inadvertent high-voltage application and may be safely opera- ted potentials uP +30 volts An R/c network guards the inputs against the effects switch bounce . Each input circui followed by an inverting Schmitt trigger. J9 0b order affect change the inputs ranging from duration 100 milliseconds . status logic "0" applied any +2 volts and having minimum LRC FC; 'Je Inter Iocking Three Pushbutton Control_Legic 0ig 1.1 7*13 Jdni The function the three con trol inputs pins and can be compared that bank three interlocking pushbutton switches where the operation any one switch causes the other two release.

@S10v 2niO€- This operation achieved the following way u2 BCD decimal decoder , used a5 priority decoder . Of the four available binary inputs only the first three are being used, namely (pin 15) , (pin 14) and (pin 13) . As these inputs are individually addressed with logic "1" level originating from the outputs u1 , the decoder wili produce logic "0" decimal output Signal output (pin 2) , output (pin output (pin 5) .

more than one input addressed simultaneously , no decoder output wili result. The three decimal outputs are combined via an OR gate consisting CR9 CRIO and CRII, the output which triggers one-shot multivibrator configured from two the four gates contained u3 _ negative-going pulse about 20 milliseconds duration generated u3 pin Routed via CR12 this pulse feeds the CLEAR inputs Ris the type latches U4A, U4B and USA .

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M202 LOGIc LATCH_MQDULE Aside from clearing the three Iatches the negative-going OUEPuIs generated pin u2 wili preset the corresponding Iatch resulting logic "1" at the "0" output the particular Iatch (pins 15/16 11/12) . Cif)" 2 When at logic each the "0" outputs drives [Wo separate transistors into turation, and 02 the case ULA . The collectors these transistors are brought out the module connectors via current limiting resistors Each these output termi- nals capable sinking maximum current MA from volt source and may be used for control tally purposes Vc3ino3 Lnitial_Reset bns noi*8?i 098 vbon: When power initially applied the combination C7 , R17 , CR13 and CR14 wil puli down the CLEAR inputs U4A U4B and USA until C7 fully charged= thus ensuring that the three Iatches are the "OFF" state and through 06 are non- ~conducting.

EAf^ 2]J49, 37" Alternate Action Logic 2onojobii0 00[ 0ou:, '0 The input circuit pin inputs described above. ing Schmitt triggers the module connector identical the followed by [wo series-connected invert- When Pin addressed with logic "0" ground input negative-going voltage will appear at the clock input (pin u5B _ The B-section u5 configured J-K flip-flop and will change state every time negative-going input transition takes Place Both the "0" as weli as the "0" output are followed by transistor switch identica the ones described earlier _ separate reset circuit, consisting C6 R12 and CRIS, clears USB when power initially applied.

the cleared reset state, 08 conducting and 07 switched off When driving 40 MA load from any the control outputs the voltage the module output terminals wili be less than volt. 92 Q9? Steering Network J0 J1: inoj Mg70i (i|Lr 0^/02 M1Bp seperate and independent steering network, consisting CRI7 through CR2I incorporated into the module. may be used for OR-gating and/or branching the controi common potential 1-2

M202 Logic LATCH MODULE Aside from clearing the three Iatches, the negative-going OUtPuts generated at pin 2, 3 or of u2 wili preset the corresponding Iatch, resulting in logic "1" at the "0" output of the particular Iatch (pins 15/16 or 11/12) 17 '( - J0; 630iv0n0 7t31si GQyi CIf > '.35 37 €0751 7D v'e7o ) 'ph^ When at logic "" each of the "0" outputs drives [Wo separate transistors into sa turation, i.e 01 and 02 in the case of ULA The collectors of these transistors are brought out [0 the module connectors via current limiting resistors Each of these OUtPut termi- nals is capable of sinking maximum current of 40 MA from 24 volt source and may be used for control or tally purposes 2). 4"| "u=s" U" 6= JJen: 0V 42| Bmn OFC7" L = ^ "(Fnos ' ~1 ] Initial Reset F0 4' ja #a P;6 noi'83ilacb #2R'in -7E'7 {F9jevbsn: 'c7 206 ~J 07B44" 4"W'_0 3.9 na 2 4< V Oc- 2" 4 QU 2 _ 'n90C :1 C $ When power is initially applied, the combination of C7 , R17 , CRI3 and CRI4 wili pul / down the CLEAR inputs of ULA , U4B and USA until C7 is fully charged, thus ensuring that the three Iatches are in the "OFF" state and 01 through 06 are non-conducting. Ve 0I 7807 } r | ~J*v = A bne L"'^ ereaBn 2) ur, 77' T4 Alternate Action Logic 1onojcbi0 O0t T0 0o "`. The input circuit at pin of the module connector is identical t0 the inputs described above. It is followed by [Wo series-connected invert- ing Schmitt triggers _ 2, !iQ 2iJoni P_"4 | ~h ? AF " A 7o 'Jat 47,47 1" no:aieL9 Bni4-o1791f: 9474' Kic Anba 04 3n" 08 +onrot? When Pin P is addressed with logic "0" or ground input, negative-going voltage wili appear at the clock input (pin 6 ) of UsB E" '0i :` RJL Oo Tfcc 4~ T The B-section of u5 is configured a5 J-K flip-flop and wiii change state every time negative-going input transition takes place . Both the "0" as weli as the "0"output are followed by transistor switch, identical to the ones described earlier. r'C ! '3 - 0i 0 Mo7 C7i' snlei-0 3 20| beazgabc L Yuocl 'd : separate reset circuit, consisting of C6, R12 and CRIS, clears USB when power is initially applied . In the cleared Or reset state, 08 is conducting and 07 is switched off. 292:9* @ _ L O^ 9 O When driving 40 MA Ioad from any of the control outputs, the voltage at the module output terminals wili be less than volt. Fd 7328/-1 OjT 0 Iq"O 9J Do u Oia3 Q9J Steer ing Network ~R0 "uo? 4F" 'o 0wa {o1 tojue"iric , ~%"/ : " NC ' : 4JU0 Zcno-JZ'^'t cf #Uc_L To 92/JQ 2"ce-"vi1dpSn seperate and independent steering network, consisting of CR17 through CR2I is incorporated into the module. It may be used for OR-gating and/or branching of the control common potential 1-2

WAAD-BECK SYSTEms LTD_ INTEGRATED CIRCUII_DAIA 24042 BCD IO DECIMAL DECODER The 74c42 one-of-ten decoder is monolithic CMOS circuit This decoder Produces logic '0 at the output ;ofreseonding to four bit binary input from zero to nine, and Togic 1 at the other outputs For binary inputs from ten to fifteen a11 outputs are logic '1' OUTPUtS Vcc 16 15 14 13 12 11 10 TOP VIEW GND OUTPUTS Inputs outputs 0 1 2 3 4 5 6 7 8 9 TRUth TABLE D C B A 2 1 1 i & 1 1 1 { 0 8 8 i L i 1 ; H 1 74042

WAAD-BECX Systems LTD_ INTEGRATED CIRCUII_DAIA 14C16 DUAL J-K FLIP-FLOP WIIH CLEAR AND_PRESET The 74c76 J-K flip-fTop is monolithic CMOs circuit Each flip- flop has independent J , K clock, clear and preset inputs a$ we11 a $ Q and W outputs The flip-flops are edge sensitive to the clock input and change s tate on the negative going transition 0 f the clock pulses Clear or preset i5 independent 0 f the clock and is accomplished by Tow Teve] on the respective input. 16 CLOCK A KA PRESET A CLEAR Q4 CLOCK CLEAR A 64 PRESET JA GND Vcc Kb PRESET CLOCK Q8 CLOCK 10 PRESET B CLEAR Q8 CLEAR B Je TOP VIEW logic "0" on clear sets Q to Togic "0" A logic "0" on preset sets Q t0 logic Note I: Note 2: tn tn+1 Truth TABLE Qn 1 0 1 Qn tn bit time before clock pulse tn+l bit time a fter clock pulse Preset Clear Qn lQn 0 0 0 1 1 0 8 Ii Lan #No change in output from previous state 74C76

WARD-BECX SYSTEMS LTD_ OTJ emetey 4Ja8-OAAW PARIS LIST M202 LOGIC LAICH_MODULE PARI DESCRIPIION MFG MEG PART MUMBER C1 C2 C3 C4 c5 Capacitor 0 . 1 uF/35 Kemet T3904104M035a5 18 5 cq92-MC-222m 3 2200 PF Aselco C6 C7 c8 c9 C10 22 uF/25 Kemet T3900226m025AS Tc T390B105M0 354 T3900475m035as X.F485= V 7 uF/35 V 281 ( fi9 tA 70j?/ 2#9 K8 31 69 ;9 2 , CRI CR2 CR3 CR4 CRS Diode Fa irchild 1n4148 54 8 M IS 8 4 0 A 0 [9 CR6 CR7 CR8 CR9 CR10 0 i [ $ S6 c Ix #69 2 ] 9 CR11 CR12 CR13 CR14 CR1S 0 ! 9 5{3 84 9 2 !A 05S CR16 CR17 CR18 CR19 CR2O Motorola XS XS 1n4003 4S SaS X $ SY: SXS ;'9 -3r {Sf 4 5 4 2s8 CR21 3-1

WAAD-BECX SYsTems LTD OTJ emateyz XW3B-OAAW PARIS LIST M202 LOGIC LAICH_MQDULE PART DESCR[PTION Transistor 8 2 3 Q5 HS -S-Jm t0j 06 ' Q7 Q8 CcE ? {^-^ o"- aCjre " 37K MFG MFG_PART NUMBER JsmisX Nationa 1 2n3569 3 0 3 3 ~[ i Cj'9? % J0 Ucss 19393 L:72 67 26 `u 25 ,70 5,$ RI R2 R3 R4 RS Resistor #w 5% 47k 47k 8w[ 4 47k 47k 470k Philips s00 ; Q I93 30 : 293 17 7 (7) R6 R7 R8 R9 R10 470k 470k 470k 47k 10k 0 ^ ) T7, 34- € v " "; R1l R12 R13 R14 R15 47k 47k 47k 47k 47k [[ ; , 47 Ei 7 ` P153 2[) ) R16 R17 R18 R19 R20 47k 47k 2k2 2k2 2k2 0 f 4J TiR ` 6[9j [ 2 - 6S/; R2 1 R22 R23 R24 R25 2k2 2k2 2k2 2k2 2k2 >' 3-2

WAAD-BECK SYSTEMS LTD PARIS LISI M202 LOGIC LAICH_MQDULE PART DESCRIPIION MFG MFG PART NUMBER R26 R27 R28 R29 R30 Resistor Sw 5% 4k7 4k7 4k7 4k7 4k7 Philips R31 R32 R33 R34 R35 4k7 4K7 4k7 Resistor Iw 5% 100 4.7 R36 R37 R38 R39 R40 100 4.7 100 4 4 R41 4.7 Integrated circuit Nationa] Mm74c14n MM74C42n MMzacqon 4 U6 Voltage Regulator Lm340T-12 WBS recommends the use of replacement parts made by the specified manufacturers for continued optimum equipment performance 3-3

P34 NOTES ALL resistors ARe Xw 5 % ALL CapAciTORS IN Af UNLESS specified Otherwise 2 LAST COMPONENT DESigNaTiONs Are cio Cr 2i 08,RA1,U6 2 UsE PcB 9-102 7c A1 TALLY rib ioo 'hw Qi 2N3569 2kz Rz6 +i2v 74-76 Ri 47k - Cri Ri3 47k Rss 74614 3 A2 CDNTROL crs in4l4B Rs Atok 47 #w Q2 Znss64 Inal

MZOZ LOGIC LATCH MODULE

PART DESCRIPT ION , '" • ", PART NUMBER Cl Cap aci to r o. 1 uf n S K••l t T390AI04M03SAS C2 • • • C3 • • • • • • • • " C5 • • ZZDO p' , Aseleo CQ9Z -HC-ZZZM ZZ uf/Z5 h.lt T3900ZZ6MOZ5AS " C7 C8 • • • I uf/3S V , • • • T390 B10 5KO35A5 cs • 4 . 7 uFnS • T39 0 D47 5MO 35AS Cl. • • • •

CR! Ofo de f e lrell l1 d I N4 14 8 CR2 • • • CR3 • • • CR4 • • • CR5 • • • • • • '" CR7 CRB • • • • • • • • • cas CliO • • • CRt I • • • CR IZ • • • CR13 • • • CRt. • • • CR I 5 • • • CRI6 • Motoro la 1N4 0 0 3 CRt7 • • • CRI8 • • • CR I9 • • • • • • a

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CR2 1 • • • BS W :// tp ht

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WA~O ·BEC K S YSTEMS LTO .

PART S LI ST

M20 2 LOGI C L AT C ~ MOOULE

PART DESCR[PTI ON HF G MFG PART NU MBER

QI Trllnsistor Nati onal 2N 35 69 Q2 0 0 0

QJ 0 0 0

0 0 0 Q' 0 0 0 Q' 0 0 0 Q' Q7 0

0 0

0 0

0 Q'

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" RJ R4 0

0 m m 0

0

0 R5 0 47 01< 0 0 R6 47 01< 0 0 R7 47 01:: RB 0 47 01< 0

R9 0 m 0

RI O 0 10K 0

RlI 0 m 0

Rl2 0 m 0

RlJ 0 m 0

RI' 0 m 0

RI ' 0